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? semiconductor components industries, llc, 2011 october, 2011 ? rev. 6 1 publication order number: ncp1532/d ncp1532 dual output step-down converter 2.25 mhz high-efficiency, out of phase operation, low quiescent current, source up to 1.6 a the ncp1532 dual step down dcdc converter is a monolithic integrated circuit dedicated to supply core and i/o voltages of new multimedia design in portable applications powered from 1 ? cell li ? ion or 3 cell alkaline / nicd / nimh batteries. both channels are externally adjustable from 0.9 v to 3.3 v and can source totally up to 1.6 a, 1.0 a maximum per channel. converters are running at 2.25 mhz switching frequency which reduces component size by allowing the use of small inductor (down to 1 h) and capacitors and operates 180 out of phase to reduce large amount of current demand on the battery. automatic switching pwm/pfm mode and synchronous rectification offer improved system efficiency. the device can also operate into fixed frequency pwm mode for low noise applications where low ripple and good load transients are required. additional features include integrated soft ? start, cycle ? by ? cycle current limit and thermal shutdown protection. the device can also be synchronized to an external clock signal in the range of 2.25 mhz. the ncp1532 is available in a space saving, ultra low profile 3x3 x 0.55 mm 10 pin dfn package. features ? up to 97% efficiency ? 50 a quiescent current ? synchronous rectification for higher efficiency ? 2.25 mhz switching frequency, 180 out of phase ? sources up to 1.6 a, 1.0 a maximum per channel ? adjustable output voltage from 0.9 v to 3.3 v ? mode selection pin: eco mode or low noise mode ? 2.7 v to 5.5 v input voltage range ? thermal limit protection ? short circuit protection ? all pins are fully esd protected ? this is a pb ? free device typical applications ? cellular phones, smart phones and pdas ? digital still cameras ? mp3 players and portable audio systems ? wireless and dsl modems ? portable equipment pin connection marking diagram http://onsemi.com udfn10 mu suffix case 506at 1532 aa aalyw fb1 fb2 en1 vin sw1 en2 sw2 110 2 3 4 9 8 7 gnd 5 mode/ sync 6 por (top view) udfn10 aa = assembly location (may be 1 or 2 characters) l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) device package shipping ? ordering information ncp1532muaatxg udfn10 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
ncp1532 http://onsemi.com 2 figure 1. ncp1532 typical application note: exposed pad of udfn10 package ? named pin11 ? must be connected to system ground. 3 5 2 6 9 11 4 1 8 7 10 vin gnd en1 mode/sync en2 sw1 fb1 sw2 fb2 por 2.2 h 10 f 2.2 h por vout1 vout2 10 f on off on off on off vin vin or vout 2.25 mhz range 18pf 18pf pin function description pin pin name type description 1 fb1 analog input feedback voltage from the output 1. this is the input to the error amplifier. 2 en1 digital input enable for converter 1. this pin is active high (higher than 1.2 v) and is turned off by logic low (lower than 0.4 v. do not leave this pin floating. 3 vin analog / power input power supply input for the pfet power stage, analog and digital blocks. the pin must be decoupled to ground by a 10 f ceramic capacitor. 4 sw1 analog output connection from power mosfets of output 1 to the inductor. 5 gnd analog ground this pin is the ground reference for the analog section of the ic. the pin must be connected to the system ground by 10 f low esr ceramic capacitor. 6 mode/sync digital input combination mode selection and oscillator synchronization. if this pin is low, the regulator runs in automatic switching pfm/pwm. with a high level (equal or lower analog input voltage), the converter runs in pwm mode only. this pin can be also syn- chronized to an external clock in the range of 2.25 mhz; in this case the device runs in pwm mode only. insert the clock before enabling the part is recommended to force external synchronization. do not let this pin floating. following rule is being used: ?0?: eco mode, automatic switching pfm/pwm, 180 out of phase. ?1?: low noise, forced pwm mode, 180 out of phase. ?clk?: external synchronization, forced pwm mode, 0 in phase. 7 sw2 analog output connection from power mosfets of output 2 to the inductor. 8 por digital output power on reset. this is an open drain output. this output is shutting down when each output voltages are less than 90% of their nominal values and goes high after 120 ms when active outputs are within regulation. a pullup resistor around 500k should be connected between por and v in , v out1 or v out2 depending on the supplied device. 9 en2 digital input enable for converter 2. this pin is active high (higher than 1.2 v) and is turned off by logic low (lower than 0.4 v). do not let this pin floating. 10 fb2 analog input feedback voltage from the output 2. this is the input to the error amplifier. 11 exposed pad power ground this pin is the ground reference for the nfet power stage of the ic. the pin must be connected to the system ground and to both input and output capacitors.
ncp1532 http://onsemi.com 3 block diagram figure 2. simplified block diagram 1 2 3 4 5 10 9 8 7 6 uvlo thermal shutdown voltage reference logic control logic control ea1 vref vref ea2 ea1 ea2 oscillator ramp generator pwm/pfm control pwm/pfm control q1 q2 q3 q4 vin vin ilimit ilimit avin avin pvin pvin fb1 en1 vin sw1 gnd fb2 en2 sw2 mode/sync por 0 180
ncp1532 http://onsemi.com 4 maximum ratings rating symbol value unit minimum voltage all pins v min ? 0.3 v maximum voltage all pins (note 1) v max 7.0 v maximum voltage en1, en2, mode v max v in + 0.3 v thermal resistance junction ? to ? air (udfn10 package) thermal resistance using recommended board layout (note 8) r ja 200 40 c/w operating ambient temperature range (notes 6 and 7) t a ? 40 to 85 c storage temperature range t stg ? 55 to 150 c junction operating temperature (notes 6 and 7) t j ? 40 to 150 c latchup current maximum rating t a = 85 c (note 4) other pins l u 100 ma esd withstand voltage (note 3) human body model machine model v esd 2.0 200 kv v moisture sensitivity level (note 5) msl 1 per ipc stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. maximum electrical ratings are defined as those values beyond which damage to the device may occur at t a = 25 c 2. according jedec standard jesd22 ? a108b 3. this device series contains esd protection and exceeds the following tests: human body model (hbm) per jedec standard: jesd22 ? a114 machine model (mm) per jedec standard: jesd22 ? a115 4. latchup current maximum rating per jedec standard: jesd78. 5. jedec standard: j ? std ? 020a. 6. in applications with high power dissipation (low v in , high i out ), special care must be paid to thermal dissipation issues. board design considerations ? thermal dissipation vias, traces or planes and pcb material ? can significantly improve junction to air thermal resistance r ja (for more information, see design and layout consideration section). environmental conditions such as ambient temperature ta b rings thermal limitation on maximum power dissipation allowed. the following formula gives calculation of maximum ambient temperature allowed by the application: t a(max) = t j(max) ? (r ja x p d ) where t j is the junction temperature, p d is the maximum power dissipated by the device (worst case of the application), and r ja is the junction ? to ? ambient thermal resistance. 7. to prevent permanent thermal damages, this device include a thermal shutdown which engages at 180 c (typical). 8. board recommended udfn10 layout is described in layout considerations section.
ncp1532 http://onsemi.com 5 electrical characteristics (typical values are referenced to t a = +25 c, minimum and maximum values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted, operating conditions v in = 3.6 v, v out1 = v out2 = 1.2 v, unless otherwise noted). rating conditions symbol min typ max unit input voltage input voltage range v in 2.7 ? 5.5 v quiescent current, no switching, no load no load mode/sync = gnd i q ? ? 50 60 70 ? a standby current en1 = en2 = gnd i stb ? 0.3 1.0 a under voltage lockout v in falling v uvlo 2.2 2.4 2.55 v under voltage hysteresis v uvloh ? 100 ? mv analog and digital pin positive going input high voltage threshold en1, en2, mode/sync v ih 1.2 ? ? v negative going input high voltage threshold en1, en2, mode/sync v il ? ? 0.4 v digital threshold hysteresis en1, en2, mode/sync v hys ? 100 ? mv external synchronization (note 11) minimum maximum mode/sync f sync ? ? 1.8 3.0 ? ? mhz power on reset (note 9) power on reset threshold v out falling v port ? 89% ? v power on reset hysteresis v porh ? 3% ? v power on reset delay (see page 12) t por ? 116 ? ms output performances feedback voltage threshold fb1, fb2 v fb ? 0.6 ? v minimum output voltage v out ? 0.9 ? v maximum output voltage v out ? 3.3 ? v output voltage accuracy (note 10) room temperature overtemperature range v out ? ? 3% 1% 2% ? +3% % output voltage load regulation ncp1532muaatxg overtemperature load = 100 ma to 600 ma v loadr ? ? 0.6 ? % load transient response rise/falltime 1 s 10 ma to 100 ma load step (pfm to pwm mode) 200 ma to 600 ma load step (pwm to pwm mode) v loadt ? ? 40 85 ? ? mv output voltage line regulation load = 100 ma v in = 2.7 v to 5.5 v v liner ? 0.05 ? % line transient response load = 100 ma 3.6 v to 3.2 v line step (falltime = 50 s) v linet ? 6.0 ? mv pp output voltage ripple i out = 0 ma i out = 300 ma v ripple ? ? 8.0 3.0 ? ? mv pp soft ? start time time from en to 90% of output voltage t start ? 230 350 s switching frequency f sw 1.8 2.25 2.7 mhz duty cycle d ? ? 100 %
ncp1532 http://onsemi.com 6 electrical characteristics (typical values are referenced to t a = +25 c, minimum and maximum values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted, operating conditions v in = 3.6 v, v out1 = v out2 = 1.2 v, unless otherwise noted). rating unit max typ min symbol conditions power switches high ? side mosfet on ? resistance r onhs ? 400 ? m low ? side mosfet on ? resistance r onls ? 300 ? m high ? side mosfet leakage current i leakhs ? 0.05 ? a low ? side mosfet leakage current i leakls ? 0.01 ? a protection dc ? dc short circuit protection peak inductor current i pk 1.2 1.6 ? a thermal shutdown threshold t sd ? 180 ? c thermal shutdown hysteresis t sdh ? 40 ? c 9. refer to power on reset section for more information. 10. the overall output voltage tolerance depends upon the accuracy of the external resistor (r1 and r2). 11. guaranteed by design.
ncp1532 http://onsemi.com 7 table of graphs typical characteristics for step down converter figure efficiency vs. output current 3, 4, 5, 6, 7, 8 i q on quiescent current, pfm no load vs. input voltage 11 i q off standby current, en low vs. input voltage 10 f sw switching frequency vs. ambient temperature 16 v loadr load regulation vs. load current 13 v loadt load transient response 14, 15 v liner line regulation vs. output current 12 t start soft start 18 i pk short circuit protection 19 v uvlo under voltage lockout threshold vs. ambient temperature 20 v il , v ih enable threshold vs. ambient temperature 21 figure 3. efficiency vs. output current (v in = 3.6 v, v out1 = 1.8 v, v out2 = 1.8 v, temperature = 25 c) mode/sync pin = gnd 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 eff (%) iout1 (ma) iout2 (ma) 0.9 ? 0.95 0.85 ? 0.9 0.8 ? 0.85 0.75 ? 0.8 0.7 ? 0.75
ncp1532 http://onsemi.com 8 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 600 i out1 , output current (ma) efficiency (%) figure 4. efficiency vs. output current v in = 3.6 v, v out1 = 1.2 v, en2 = gnd pwm pfm 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 efficiency (%) i out1 , output current (ma) figure 5. efficiency vs. output current v in = 3.6 v, v out1 = 1.2 v, en2 = gnd pwm pfm efficiency (%) 100 95 90 85 80 75 70 65 60 55 50 45 40 0 1000 800 600 400 200 i out1 , output current (ma) figure 6. efficiency vs. output current v in = 3.6 v, v out1 = 1.2 v, en2 = gnd, temperature = 25 c ? 40 c 85 c 25 c 100 95 90 85 80 75 70 65 60 55 50 45 40 efficiency (%) 0 1000 800 600 400 200 i out1 , output current (ma) figure 7. efficiency vs. output current v out1 = 1.2 v, en2 = gnd, temperature = 25 c v bat = 5.5 v 3.6 v 2.7 v i out1 , output current (ma) figure 8. efficiency vs. output current v in = 3.6 v, en2 = gnd, temperature = 25 c 0 1000 800 600 400 200 100 95 90 85 80 75 70 65 60 55 50 45 40 efficiency (%) v out = 1.2 v v out = 3.3 v v in , input voltage (v) 5.5 3.0 3.5 4.0 4.5 5.0 100 efficiency (%) figure 9. maximum efficiency vs. input voltage v out1 = v out2 = 3.3 v i out1 = i out2 = 100 ma 99 98 97 96 95 94 93 92 91 90
ncp1532 http://onsemi.com 9 2.5 5.0 4.5 4.0 3.5 3.0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 5.5 v in , input voltage (v) figure 10. standby current vs. input voltage v in = 3.6 v, en1 = en2 = gnd, temperature = 25 c i sb , standby current ( a) v in , input voltage (v) figure 11. quiescent current vs. input voltage v in = 3.6 v, v fb1 = v fb2 = 0.8 v 2.5 5.0 4.5 4.0 3.5 3.0 5.5 60 55 50 45 40 35 30 25 20 i q , quiescent current ( a) buck1 buck1 & buck2 buck2 ? 40 c 85 c 25 c v in , input voltage (v) figure 12. line regulation v out1 = 1.2 v, i out1 = 100 ma, en2 = gnd 5.2 3.2 3.7 4.2 4.7 2.7 20 15 10 5 0 ? 5 ? 10 ? 15 ? 20 line reg (mv) ? 40 c 25 c 85 c i out1 , output current (ma) figure 13. load regulation v in = 3.6 v, v out1 = 1.2 v, en2 = gnd 0 20 15 10 5 0 ? 5 ? 10 ? 15 ? 20 200 400 600 800 1000 load regulation (mv) figure 14. load transient and crosstalk, v in = 3.6 v v out1 = 1.2 v, i out1 from 200 ma to 600 ma v out2 = 1.2 v, i out2 = 600 ma, 8 mv crosstalk figure 15. load transient and crosstalk, v in = 3.6 v v out1 = 1.2 v, i out1 from 200 ma to 600 ma v out2 = 1.2 v, i out2 = 600 ma, 8 mv crosstalk
ncp1532 http://onsemi.com 10 temperature ( c) figure 16. switching frequency vs. temperature f sw , drift (%) ? 50 100 25 0 ? 25 125 5 4 3 2 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 75 50 v bat = 5.5 v 3.6 v 2.7 v figure 17. external synchronization, f sync = 2.93 mhz figure 18. soft ? start typical behavior v in = 3.6 v, v out1 = v out2 = 1.2 v, i out1 = i out2 = 600 ma figure 19. current peak inductor protection v in = 3.6 v, v out1 = 1.2 v, i out1 short to gnd, en2 = gnd uvlofall uvlorise 2.5 2.49 2.48 2.47 2.46 2.45 2.44 2.43 2.42 2.41 2.4 2.39 2.38 2.37 2.36 2.35 temperature ( c) figure 20. uvlo thresholds v in = 3.6 v, i out1 = i out2 = 2 ma uvlo threshold (v) ? 50 100 25 0 ? 25 125 75 50 ? 50 100 25 0 ? 25 125 75 50 enable threshold (v) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 temperature ( c) figure 21. enable thresholds v in = 3.6 v, i out1 = i out2 = 2 ma v ih v il
ncp1532 http://onsemi.com 11 dc/dc operation description detailed description the ncp1532 uses a constant frequency, current mode step ? down architecture. both the main (p ? channel mosfet) and synchronous (n ? channel mosfet) switches are internal. the output voltages are set by the external resistor divider in the range of 0.9 v to 3.3 v and can source 1600 ma totally depending on device option. the ncp1532 works with two modes of operation; pwm/pfm depending on the current required. in pwm mode, the device can supply voltage with a tolerance of 3% and 90% efficiency or better. lighter load currents cause the device to automatically switch into pfm mode to reduce current consumption (i q = 50 a) and extended battery life. for low noise applications, by pulling the mode/sync pin to v in , the device operates in pwm mode only. additional features include soft ? start, undervoltage protection, current overload protection and thermal shutdown protection. as shown on figure 1, only six external components are required for implementation. the part uses an internal reference voltage of 0.6 v. it is recommended to keep ncp1532 in shutdown until the input voltage is 2.7 v or higher. to reduce power demand on the battery, the two dc ? dc operates out of phase. this reduces significantly spikes on v in line. using external synchronization, the two channels are working on same signal phase. see mode/sync section for more information. pwm operating mode in this mode, the output voltage of the device is regulated by modulating the on ? time pulse width of the main switch q1 at a fixed 2.25 mhz frequency. the switching of the pmos q1 is controlled by a flip ? flop driven by the internal oscillator and a comparator that compares the error signal from an error amplifier with the sum of the sensed current signal and compensation ramp. the driver switches on and off the upper side transistor (q1) and switches the lower side transistor in either on state or in current source mode. at the beginning of each cycle, the main switch q1 is turned on by the rising edge of the internal oscillator clock. the inductor current ramps up until the sum of the current sense signal and compensation ramp becomes higher than the error amplifier?s voltage. once this has occurred, the pwm comparator resets the flip ? flop, q1 is turned off while the synchronous switch q2 is turned on. q2 replaces the external schottky diode to reduce the conduction loss and improve the efficiency. to avoid overall power loss, a certain amount of dead time is introduced to ensure q1 is completely turned off before q2 is being turned on. figure 22. pwm switching waveforms v in = 3.6 v, v out1 = v out2 = 1.2 v, i out1 = i out2 = 100 ma pfm operating mode under light load conditions, the ncp1532 enters in low current pfm mode of operation to reduce power consumption. the output regulation is implemented by pulse frequency modulation. if the output voltage drops below the threshold of pfm comparator a new cycle will be initiated by the pfm comparator to turn on the switch q1. q1 remains on during the minimum on time of the structure while q2 is in its current source mode. the peak inductor current depends upon the drop between input and output voltage. after a short dead time delay where q1 is switched off, q2 is turned in its on state. the negative current detector will detect when the inductor current drops below zero and sends the signal to turn q2 in current source mode to prevent a too large deregulation of the output voltage. when the output voltage falls below the threshold of the pfm comparator, a new cycle starts immediately.
ncp1532 http://onsemi.com 12 figure 23. pfm switching waveforms v in = 3.6 v, v out1 = v out2 = 1.2 v, i out1 = i out2 = 0 ma soft ? start the ncp1532 uses soft ? start to limit the inrush current when the device is initially powered up or enabled. soft ? start is implemented by gradually increasing the reference voltage until it reaches the full reference voltage. during startup, a pulsed current source charges the internal soft ? start capacitor to provide gradually increasing reference voltage. when the voltage across the capacitor ramps up to the nominal reference voltage, the pulsed current source will be switched off and the reference voltage will switch to the regular reference voltage. cycle ? by ? cycle current limitation from the block diagram (figure 2), an i lim comparator is used to realize cycle ? by ? cycle current limit protection. the comparator compares the sw pin voltage with the reference voltage, wh ich is biased by a constant current. if the inductor current reaches the limit, the ilim comparator detects the sw voltage falling below the reference voltage and releases the signal to turn off the switch q1. the cycle ? by ? cycle current limit is set at 1600 ma (nom). low dropout operation the ncp1532 offers a low input to output voltage difference. the ncp1532 can operate at 100% duty cycle on both channels. in this mode the pmos (q1) remains completely on. the minimum input voltage to maintain regulation can be calculated as: v in (min) v out (max) (i out (r ds(on) _r inductor ) (eq. 1) ? v out : output voltage (v) ? i out : maximum output current ? r ds(on) : p ? channel switch r ds(on) ? r inductor : inductor resistance (dcr) power on reset the power on reset (por) is pulled low when either active converter is out of 89% of their regulation. when active outputs are in the range of regulation, a counter starts to provide the por signal with a delay equal to 262,144 clock cycles. the delay is depending on internal clock frequency. if only one channel is active, por runs only on the active output until the other converter is disabled. when this regulator becomes enabled, por drops down until the second output reaches its voltage range. a pullup resistor (around 500 k) is needed to this open drain output. this resistor may be connected to v in or to an output voltage of one regulator if the device supplied cannot accept v in on the io. in the case of por being tied to v in , por is high when ncp1532 is off. in the case of por being tied to v out , por is low when ncp1532 is off. figure 24. por behavior vs. v out1 leave the por pin unconnected when not used. mode selection and frequency synchronization the mode/sync pin is a multipurpose pin which provides mode selection and frequency synchronization. when this pin is connected to ground, auto ? switching pfm/pwm mode is selected which provides the best efficiency at light load and quiescent current with a good ripple compromise (less than 8 mv). connecting this pin to v in enables pwm mode of operation, which provides the best low noise solution, low ripple and low load transient performance. ncp1532 can also be synchronized to an external clock signal in the range from internal switching frequency to 3.0 mhz. lower frequency causes the part enters one time in pfm/pwm mode, and the other time in pwm mode. insert the clock before enabling the part is recommended to force external synchronization. this function allows synchronizing ncp1532 with another switching device such as the switching output of another dc to dc converter forced in pwm mode. this decreases noise dispersion generated by the converters.
ncp1532 http://onsemi.com 13 undervoltage lockout the input voltage v in must reach 2.4 v (typ) before the ncp1532 enables the dc/dc converter output to begin the start up sequence (see soft ? start section). the uvlo threshold hysteresis is typically 100 mv. shutdown mode when the en pin has applied voltage of less than 0.4 v, the ncp1532 will be disabled. in shutdown mode, the internal reference, oscillator and most of the control circuitries are turned off. therefore, the typical current consumption will be 0.3 a (typical value). applying a voltage above 1.2 v to en pin will enable the dc/dc converter for normal operation. the device will go through soft ? start to normal operation. thermal shutdown internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. if the junction temperature exceeds 180 c, the device shuts down. in this mode all power transistors and control circuits are turned off. the device restarts in soft start after the temperature drops below 140 c. this feature is provided to prevent catastrophic failures from accidental device overheating. short circuit protection when one output is shorted to ground, the device limits the inductor current. the duty ? cycle is minimum and the consumption on the input line is 300 ma (typ). when the short circuit condition is removed, the device returns to the normal mode of operation. application information output voltage selection the output voltage is programmed through an external resistor divider connected from v out to fb then to gnd. for low power consumption and noise immunity, the resistor from fb to gnd (r2) should be in the [100 k 600 k] range. if r2 is 200 k given the v fb is 0.6 v, the current through the divider will be 3.0 a. the formula below gives the value of v out , given the desired r1 and the r2 value: v out v fb 1 r1 r2 (eq. 2) ? v out : output voltage (v) ? v fb : feedback voltage = 0.6 v ? r1: feedback resistor from v out to fb ? r2: feedback resistor from fb to gnd input capacitor selection in pwm operating mode, the input current is pulsating with large switching noise. using an input bypass capacitor can reduce the peak current transients drawn from the input supply source, thereby reducing switching noise significantly. the capacitance needed for the input bypass capacitor depends on the source impedance of the input supply. the maximum rms current occurs at 50% duty cycle with maximum output current, which is io, max/2. for ncp1532, a low profile ceramic capacitor of 10 f should be used for most of the cases. for effective bypass results, the input capacitor should be placed as close as possible to the vin pin. capacitors with 10 v rated voltage are recommended to avoid dc bias ef fect over input voltage range. table 1. list of input capacitor murata grm21br61a106 10 f taiyo yuden jmk212bj106 10 f tdk c2012x5r1a106 10 f output l ? c filter design considerations the ncp1532 is built in 2.25 mhz frequency and uses current mode architecture. the correct selection of the output filter ensures good stability and fast transient response. due to the nature of the buck converter, the output l ? c filter must be selected to work with internal compensation. for ncp1532, the internal compensation is internally fixed and it is optimized for an output filter of l = 2.2 h and c out = 10 f. the corner frequency is given by: f 1 2 l c out 1 2 2.2 h 10 f 34 khz (eq. 3) the device operates with inductance value of 2.2 h. if the corner frequency is moved, it is recommended to check the loop stability depending of the accepted output ripple voltage and the required output current. take care to check the loop stability. the phase margin is usually higher than 45 .
ncp1532 http://onsemi.com 14 table 2. table 2: l ? c filter example inductance (l) output capacitor (c out ) 1.0 h 22 f 2.2 h 10 f 4.7 h 4.7 f inductor selection the inductor parameters directly related to device performances are saturation current and dc resistance and inductance value. the inductor ripple current ( i l ) decreases with higher inductance: i l v out l f sw 1 v out v in (eq. 4) ? i l : peak ? to ? peak inductor ripple current ? l: inductor value ? f sw : switching frequency the saturation current of the inductor should be rated higher than the maximum load current plus half the ripple current: i l (max) i o (max) i l 2 (eq. 5) ? i l (max): maximum inductor current ? i o (max): maximum output current the inductor?s resistance will factor into the overall efficiency of the converter. for best performances, the dc resistance should be less than 0.3 for good efficiency. table 3. list of inductor fdk mipw3226 series tdk vlf3010at series tfc252005 series taiyo yuden lq cbl2012 coil craft do1605 series lps4018 series output capacitor selection selecting the proper output capacitor is based on the desired output ripple voltage. ceramic capacitors with low esr values will have the lowest output ripple voltage and are strongly recommended. the output capacitor requires either an x7r or x5r dielectric. we recommend to place a capacitor with rated voltage much higher than the output voltage selected by the external divider. capacitors with 10 v rated voltages are recommended from 2.0 v to 3.3 v output voltages. the output ripple voltage in pwm mode is given by: v out i l 1 4 f sw c out esr (eq. 6) table 4. list of output capacitor murata grm219r61a475 4.7 f grm21br61a106 10 f taiyo yuden jmk212by475mg 4.7 f jmk212bj106mg 10 f tdk c2012x5r1a475 4.7 f c2012x5r1a106 10 f feed ? forward capacitor selection the feed ? forward capacitor sets the feedback loop response and is critical to obtain good loop stability. given that the compensation is internally fixed, an 18 pf or higher ceramic capacitor is needed. choose a small ceramic capacitor x7r or x5r or cog dielectric.
ncp1532 http://onsemi.com 15 layout considerations electrical layout considerations implementing a high frequency dc ? dc converter requires respect of some rules to get a powerful portable application. good layout is key to prevent switching regulators to generate noise to application and to themselves. electrical layout guide lines are: ? use short and large traces when large amount of current is flowing. ? keep the same ground reference for input and output capacitors to minimize the loop formed by high current path from the battery to the ground plane. ? isolate feedback pin from the switching pin and the current loop to protect against any external parasitic signal coupling. add a feed ? forward capacitor between vout and fb which adds a zero to the loop and participates to the good loop stability. a 18 pf capacitor is recommended to meet compensation requirements. a four layer pcb with a ground plane and a power plane will help ncp1532 noise immunity and loop stability. thermal layout considerations high power dissipation in small package leads to thermal consideration such as: ? enlarge the v in trace and add several vias that are connected to power plane. ? connect the gnd pin to the top plane. ? join top, bottom and each ground plane together using several free vias in order to increase dissipation capability. for high ambient temperature and high power dissipation requirements, refer to notes 7, 8, and 9 to prevent any thermal issue. vin trace sw1 trace sw2 trace vout1 trace vout2 trace pgnd en1 trace en2 trace mode /sync trace por trace fb1 trace fb2 trace gnd plane figure 25.
ncp1532 http://onsemi.com 16 package dimensions udfn10 3x3, 0.5p case 506at issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. c a seating plane d b e 0.15 c a3 a a1 2x 2x 0.15 c dim a min nom max millimeters 0.45 0.50 0.55 a1 0.00 0.03 0.05 a3 0.127 ref b 0.18 0.25 0.30 d 3.00 bsc d2 2.40 2.50 2.60 e 3.00 bsc 1.70 1.80 1.90 e2 e 0.50 bsc 0.19 typ k pin one reference 0.08 c 0.10 c 10x a 0.10 c note 3 l e d2 e2 b b 5 6 10x 1 k 10 10x 10x 0.05 c 8x 0.30 0.40 0.50 l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1532/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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